Sr. Analog RFIC Design Engineer

This position is in our Santa Clara, CA office

Primary activities include the design of RF/IF analog blocks for broadband telecommunication ICs integrated in a CMOS process. Able to perform at various levels including top-level routing and verification, the finalization of the block specifications and design to the schematic capture, the layout, test and evaluation of the prototype ICs. The candidate’s profile must show a strong emphasis on analog design and layout skills. Must be able to work independently in a small, but proficient and dynamic, analog design team.

Responsibilities:

Responsible for the design and debug at the transistor level of integrated circuit blocks / subsystems. Performs circuit design, simulation, layout and test. On demand, prepares short presentations of his/her work advancement for internal design reviews. Responsible for interacting directly with other designers and the design architect to ensure the compatibility of his/her work with the overall system. Capable of managing his/her time and effort in a small project from specifications and first design solutions to final layout circuits.

Requirements:
• M.S. degree or Ph.D. degree in Electrical Engineering with a minimum of 5 years experience in analog or mixed-mode IC design at the transistor level.
• Strong knowledge of sub-micron CMOS process (0.18um or below);
• Skill with the Cadence environment, especially layout tools. The candidate should be able to perform DRC verifications as well of debugging LVS results.
• Hands-on experience of custom layouts at transistor level for minimum parasitic effects as well as of top-level circuits for efficient performance in mixed-signal chips.
• Expert in analog baseband circuit design (active filters, amplifiers, biasing and reference circuits) typically:
– Transconductor amplifier circuits, linearization techniques,
dynamic range optimization
– Stabilities issues in multi-stages feedback loops,
– Common mode rejection techniques.
• Solid theoretical basis of transistor model;
good understanding of noise, flicker noise, offsets, mismatches and linearity issues.

Contact: To apply, please send resume to:
3900 Freedom Circle, Suite #200
Santa Clara, CA 95054
Fax to: 408-486-5615
To E-mail your resume, click here.